In digital computer arithmetic units which perform shift instructions generally, and especially double precision shifting of two data words as are contained in two registers, it is necessary for control logics to act upon the top-level shift control signals as are normally derived from instruction translation or command directives in order to effectuate the detail low-level control of a shift matrix so as to accomplish the desired result. The types of top-level shift control signals which must ultimately effect control of the shift matrix include the shift count, whether a shift is left or right, whether a circular (recirculating) shift is desired, whether shifted bit positions should be zero filled or sign filled, and whether it is the first or second pass of a double precision shift. The low-level control of the shift matrix is defined as the control of the selection of data input to the shift matrix plus the control of the amount of shifting, or shift count, to be performed on the selected data as it passes through the shift matrix.
This low-level control of the shift matrix is normally accomplished from a control site called a shift matrix control register. This shift matrix control register contains the binary encoded shift count as will control the magnitude of shift in a unidirectionally shifting shift matrix, plus selector control bits which determine which register or other quantity will be gated to the shift matrix through multiplexor logic elements called selectors. For example, the binary encoded shift count such as would control shifting of zero to fifteen bit positions in a sixteen bit shift matrix would occupy four bit positions. The number of selector control bits is dependent both upon the number of selectors connected to the shift matrix and the number of different registers or quantities controllably gated through each.
For example, to accomplish double precision shifting with selectable sign fill in a sixteen bit shift matrix two selectors--called upper and lower, each capable of selectively gating one of three quantities to the shift matrix--are required. The selector control bits are not encoded and therefore total 2.times.3=6. The total of count and selector control bits as comprise the low-level shift control of the shift matrix equals 4+6=10.
The standard logical means in computer science for translating the relative complexity of the shift control signals into the relative simplicity of the shift count and selector control, as would be held in a shift matrix control register, is the logical means of a Read Only Memory (ROM). The total of shift control signals such as shift count, left or right shift, circular shift with fill, single or double precision, an first or second pass are used to address the ROM. The signals output from the ROM are the shift matrix control signals which, when held in the shift matrix control register, are used to select data input to the shift matrix and to control the shift count within the shift matrix.
Although shift control logics consisting only of a ROM are very simple and straightforward to implement, the size of the ROM becomes large as both the number of shift control signals used for addressing the ROM and the number of output signals required from the ROM increases. A reason that the shift control signals might be numerous is that they reflect a complex shift operation such as double precision shifting or circular shifting. Such complex shift operations support a large and complex repertoire of shift instructions or commands. These more complex shift operations also require an increase in the selector control portion of the signals output from the ROM. For example, a double precision shift operation requires that the contents of two registers and a sign fill quantity each be variously gated under the control of two selectors, upper and lower, to the shift matrix. The three quantities gated times the two selectors controlled equals six shift matrix selector control signals which must be output from the ROM shift logics. This is in addition to the number of final shift count signals, such as are sufficient to control the magnitude of shifting within the unidirectional shift matrix, which also must be output from the shift control ROM.
In recognition that the ROM means of implementing shift control logics, although straightforward, requires a large number of logic elements when the shift process controlled is sophisticated, the art of computer logic design has progressed toward reducing the size requirement for the ROM.
This reduction has been accomplished by encoding the control signals output from the ROM, specifically the selector control signals which are encoded as preselector control signals. The control of a single selector's gating of the three quantities can be encoded in two output signals called preselector signals. The two preselector signals are decoded to develop up to four signals; three of which control gating of the three quantities through each selector. This limitation of the required ROM size in one dimension, through reducing the required number of output signals through encoding, obviously does nothing to reduce the large number of control signals which, by addressing the ROM shift logics, determine the other dimension of ROM size. Of course, the ROM could be eliminated altogether as an implementing means for shift logics and total custom logic circuitry could be employed. But this would be inefficient to design or fabricate.